1. Field of the Invention
The present invention relates to a semiconductor memory device such as a SRAM (Static Random Access Memory) having a hierarchical bit line structure and, more particularly, to a layout of an amplification circuit and the like on a semiconductor substrate.
2. Description of the Prior Art
A semiconductor memory device is composed of a plurality of memory cells and other circuits. Because the ratio of an area occupied by the memory cells to the total area of an LSI (Large Scale Integration) is high, there is a strong demand for a reduction in the area occupied by each of the memory cells. The same demand is also applied to a 1-port memory from and in which data is read and written via one port and to a multi-port memory from and in which data is simultaneously read and written via a plurality of ports including a read-only port.
In recent years, a memory in an ultra-small semiconductor device generation has tended to adopt a layout topology termed a horizontal cell structure or the like, in which the gate electrodes of transistors constituting memory cells are each formed in a direction perpendicular to bit lines. A multi-port memory to which a horizontal cell structure as mentioned above is applied is disclosed in, e.g., Japanese Laid-Open Patent Publication No. 2002-43441.
There is also known a memory having a hierarchical bit line structure. This type of memory has, e.g., a read amplification circuit for selecting one of signals read onto a plurality of bit lines, amplifying the selected signal, and outputting the amplified signal onto a global bit line. Amplification circuits as mentioned above are disclosed in, e.g., Japanese Laid-Open Patent Publication Nos. 2004-55130 and 2004-47003, U.S.Pat. Nos. 6,014,338 and 6,105,123, and the like.
In a conventional semiconductor memory device having a horizontal cell structure and a hierarchical bit line structure, each as mentioned above, and also having a read-only port, an N-well region in which the P-channel transistors of an amplification circuit are formed is formed to be isolated from an N-well region in which the P-channel transistors of memory cells are formed, in the same manner as in a control circuit, a column selector, a row decoder, or the like in a multi-port memory.
Specifically, a layout as schematically shown in, e.g., FIG. 9 can be considered. In the example of FIG. 9, memory cell portions M1 each including an optical dummy cell portion D1, substrate contact portions C1, N-well isolation portions S1, and an amplification circuit portion LAMP1 are provided on a semiconductor substrate. N-channel transistors constituting the individual portions are formed in a P-well region PW1, while P-channel transistors constituting the individual portions are formed in N-well regions NWA1, NWB1, NWC1, NWC2, NWD1, and NWD2. The N-well region NWA1 is isolated from the N-well regions NWC1 and NWC2 by the N-well isolation portions S1. The N-well region NWB1 is also isolated from the N-well regions NWD1 and NWD2 by the N-well isolation portions S1. In the P-well region PW1, the N-well region NWA1, and the like, substrate contacts 11 and 12 are provided
The amplification circuit portion LAMP1 is specifically constructed as shown in FIG. 10. That is, P-channel transistors P1 to P10 (PMOS transistors) are formed in the N-well regions NWA1 and NWB1, while N-channel transistors N1 and N2 (NMOS transistors) are formed in the P-well region PW1. The gate electrodes PG1 of the P-channel transistors P1 to P10 are each formed in a direction (vertical direction in FIG. 10) parallel with bit lines not shown. The gate electrodes NG1 of the N-channel transistors N1 and N2 are each formed in a direction (lateral direction in FIG. 10) perpendicular to the bit lines.
However, in the case where the N-well regions NWA1 to NWD2 are formed in isolated relation as described above, regions where the N-well isolation portions S1 and the substrate contacts 12 are provided individually are needed so that an area occupied by the entire memory relative to the total area of the semiconductor substrate tends to increase.